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Adaptive voltage scaling
Adaptive Voltage Scaling (AVS) is a closed-loop dynamic power minimization technique that reduces power based on the actual operating conditions of the chip, i.e., the power consumption is continuously adjusted during the run time of the chip. Typically the design of any chip is done in such a way that it meets most demanding application throughput requirements under worst case operating conditions. This leads to an excess margin or wastage of power because the chip usually operates under typical operating conditions. AVS is beneficial compared to the conventional Dynamic voltage scaling (DVS) approach, a commonly encountered open loop dynamic power minimization technique, because AVS eliminates the excess power margins that are present in the open loop DVS systems due to the fixed voltage-frequency relations employed in those systems.〔 In AVS technique the chip's exact process corner is determined either during the manufacturing test or during runtime and the appropriate Voltage-Frequency relationship is determined, which will be used during the dynamic voltage and frequency scaling operations. This eliminates the extra margin that will be present if the worst case operating conditions are taken into account while the chip is actually operating under typical conditions.
〔(Bharadwaj Amrutur , Nandish Mehta , satyam Dwivedi, Ajit Gupte . "Adaptive techniques to reduce power in digital circuits".Journal of low power electronics and applications , 4 july 2011. )〕〔
== Background ==
Technology scaling has enabled to design very powerful and versatile computing systems on smaller chips.As the smaller feature size allows more functions to be implemented in the same area, there is an escalation in current density and the associated power dissipation. As the demands for high processing power and clock-rates are ever increasing due to the higher integration, the power consumption and thermal performance of Integrated circuit is emerging as the limiting factor for high performance processor systems.〔Nakai.M,Akui S,Seno.k,Seki.T,Kondo.T,Hashiguchi.A,Kawahara.H,Kumano.K,Shimura.M."Dynamic voltage and frequency management for a low-power embedded microprocessor".IEEE J.''Solid State Circuit''2005,40,28-35〕〔Rabaey,''J.Low Power Design Essentials'', springer :New York ,NY,USA,2009.〕〔 Also the need for reducing the self-heating of the processor chips operating in automotive temperature environments enhances the need for solutions that reduce power dissipation .A lot of techniques can be used to transform a high-performance system into a low power system.However,minimizing power consumption in digital CMOS circuits requires a lot of design effort at system, architectural, circuit and device levels. Supply Voltage reduction technique is one of the most effective ways of reducing the power consumption.Nevertheless, one direct consequence of static supply voltage scaling is performance degradation.To maintain the desired throughput, Dynamic voltage scaling systems are used to adjust the supply voltage according to the throughput requirements . But there is still a large amount of power margin wasted in the Open-loop DVS systems and to overcome this AVS systems are being examined.〔(National Products from Texas instruments, “Adaptive voltage scaling technology, up to 60% energy savings on core operation” )〕
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